Interfacing 8255 with 8085
Description
Step 1:
Lower order of 8-bit address A0-A7 is separated from AD0-AD7 using address latch/buffer (Ex: IC 74373) and ALE signal.
The separated address lines A0-A7 are connected to A0-A7 input pins of 8255 and the separated data bus D0-D7 are connected to D0-D7 pins of 8255.
Reset out of 8085 is connected to reset pin of 8255.
Step 2:
8255 does not have internal (separate) control logic generator, hence the IO/M(bar), RD(bar) and WR(bar) control signals are not connected directly to 8255. These pins are 1st given to decoder and decoded using 3:8 decoder (Ex: IC 74138).
The generated control signals IOR(bar) and IOW(bar) are connected to RD(bar) and WR(bar) input of 8155.
Step 3:
An active low signal of chip select logic is obtained decoding remaining address lines of lower order addresses A2- A7.
Chip select logic and IO port address for this interfacing circuit are as:
Interfacing Diagram
CACKLE comment system
