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# Instruction sets

## Branching Instruction

 Opcode Operand Description JMP 16-bit address The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. Example: JMP 2034H or JMP XYZ JC Jump on Carry. CY Flag = 1 JNC Jump on no Carry CY Flag = 0 JP Jump on positive S Flag = 0 JM Jump on minus S Flag = 1 JZ Jump on zero Z Flag = 1 JNZ Jump on no zero Z Flag = 0 JPE Jump on parity even P Flag = 1 JPO Jump on parity odd P Flag= 0 CALL 16-bit address The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. Before the transfer, the address of the next instruction after CALL (the contents of the program counter) is pushed onto the stack. Example: CALL 2034H or CALL XYZ CC Call on Carry CY Flag = 1 CNC Call on no Carry CY Flag = 0 CP Call on positive S Flag = 0 CM Call on minus S Flag = 1 CZ Call on zero Z Flag = 1 CNZ Call on no zero Z Flag = 0 CPE Call on parity even P Flag = 1 CPO Call on parity odd P Flag = 0 RET The program sequence is transferred from the subroutine to the calling program. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address. RC Return on Carry CY Flag = 1 RNC Return on no Carry CY Flag = 0 RP Return on positive S Flag = 0 RM Return on minus S Flag = 1 RZ Return on zero Z Flag = 1 RNZ Return on no zero Z Flag = 0 RPE Return on parity even P Flag = 1 RPO Return on parity odd P Flag = 0 PCHL The contents of registers H and L are copied into the program counter. The contents of H are placed as the high-order byte and the contents of L as the low-order byte. RST 0-7 The RST instruction is equivalent to a 1-byte call instruction to one of eight memory locations depending upon the number. The instructions are generally used in conjunction with interrupts and inserted using external hardware. However these can be used as software instructions in a program to transfer program execution to one of the eight locations.

## The addresses of RST 0-7are

 Instruction Restart Address RST 0 0000H RST 1 0008H RST 2 0010H RST 3 0018H RST 4 0020H RST 5 0028H RST 6 0030H RST 7 0038H

## Logical Instructions

 Opcode Operand Description CMP R The contents of the operand (register or memory) are compared with the contents of the accumulator.  Both contents are preserved .  The result of the comparison is shown by setting the flags of the PSW as follows: if (A) < (reg/mem): carry flag is set if (A) = (reg/mem): zero flag is set if (A) > (reg/mem): carry and zero flags are reset Example: CMP B  or  CMP M M CPI 8-bit data The second byte (8-bit data) is compared with the contents of the accumulator. The values being compared remain unchanged. The result of the comparison is shown by setting the flags of the PSW as follows: if (A) < data: carry flag is set if (A) = data: zero flag is set if (A) > data: carry and zero flags are reset Example: CPI 89H ANA R The contents of the accumulator are logically ANDed with the contents of the operand (register or memory), and the result is placed in the accumulator.  If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY is reset. AC is set. Example: ANA B or ANA M M ANI 8-bit data The contents of the accumulator are logically ANDed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY is reset. AC is set. Example: ANI 86H XRA R The contents of the accumulator are Exclusive ORed with the contents of the operand (register or memory), and the result is placed in the accumulator.  If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: XRA B or XRA M M XRI 8-bit data The contents of the accumulator are Exclusive ORed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset.Example: XRI 86H ORA R The contents of the accumulator are logically ORed with the contents of the operand (register or memory), and the  result is placed in the accumulator.  If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: ORA B or ORA M M ORI 8-bit data The contents of the accumulator are logically ORed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: ORI 86H RLC Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position of D0 as well as in the Carry flag. CY is modified according to bit D7. S, Z, P, AC are not affected. RRC Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the position of D7 as well as in the Carry flag. CY is modified according to bit D0. S, Z, P, AC are not affected. RAL Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D7 is placed in the Carryflag, and the Carry flag is placed in the least significant position D0. CY is modified according to bit D7. S, Z, P, AC are not affected. RAR Each binary bit of the accumulator is rotated right by one position through the Carry flag. Bit D0 is placed in the Carry flag, and the Carry flag is placed in the most significant position D7. CY is modified according to bit D0. S, Z, P, AC are not affected. CMA The contents of the accumulator are complemented. No flags are affected. CMC The Carry flag is complemented. No other flags are affected. STC The Carry flag is set to 1. No other flags are affected. NOP No operation is performed. The instruction is fetched and decoded. However no operation is executed. HLT The CPU finishes executing the current instruction and halts any further execution. An interrupt or reset is necessary to exit from the halt state. Example: HLT DI The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled. No flags are affected. EI The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. After a system reset or the acknowledgement of an interrupt, the interrupt enable flip- flop is reset, thus disabling the interrupts. This instruction is necessary to re-enable the interrupts (except TRAP).

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